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I'm going to pretend the irq is asserted during the cycle indicated by the timing test program. In reality it could be asserted some time before depending on the details of the PIA edge detect circuit and the 6809 sync & priority network, but it doesn't really matter as far as the following is concerned.
In the case of the instruction lda $ff02, this instruction clears the frame sync irq by reading from the PIA. The read occurs on the last (5th) cycle of the instruction and the irq is cleared from the point of view of the 6809 by the time of the following (6th) cycle.
The clear operation has priority and prevents an irq being asserted during the cycle following lda $ff02. This is why we don't get an irq on phase 6 of the test. The irq returns on phase 7 because it is now being asserted after the clear operation.
For the instruction clr $ff02, this also clears the frame sync irq by reading from the PIA. It's a read-modify-write type of instruction and the read occurs on the 5th cycle. This suppresses an irq on the 6th cycle, and allows an irq on the 7th cycle, just like lda $ff02.
*However*
The instruction clr $ff02 is 7 cycles long and the 6809 irq input is level sensitive. This means an irq occurring during the first 6 cycles is cleared before the instruction is complete and the 6809 doesn't get to see it. i.e. an irq occurring during the first 6 cycles of clr $ff02 will not get serviced.
I've attached the latest test program. The large number of tests is making it unwieldy, so would probably benefit from a menu if it is to grow any more.