I am writing a test routine to increase two counters. Counter CHS is increased with the HS interrupt (falling edge) and the other counter (CFS) with the FS interrupt (rising edge).
First, I set the interrupts:
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ORCC #$10 ; Disable IRQ
; set hsync interrupt
;set bit 0 of P0CRB (enable FS IRQs)
;clear bit 1 of P0CRB to get IRQs on the falling edge
LDA P0CRB
ANDA #$FD
ORA #%01
STA P0CRB
;set bit 0 of P0CRA (enable HS IRQs)
;Set bit 1 of P0CRA to get IRQs on the rising edge
LDA P0CRA
ORA #%11
STA P0CRA
lda P0PDRA ; clear IRQ
lda P0PDRB ; clear IRQ
LDA P0CRB
LDX #HIRQ ; Set up entry address
STX $10D ; and store into IRQSV
ANDCC #$EF ; Enable IRQ
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HIRQ PSHS A, X
ORCC #$10 ; Disable IRQ
LDA P0CRB
BITA #$80 ; check if FS
BEQ NO_FS ; if not set...
INC CFS
NO_FS LDA P0CRA
BITA #$80 ; check if HS
BEQ NO_HS ; if not set...
INC CHS
NO_HS LDA P0PDRA ; clear HS interrupt flag
LDA P0PDRB ; clear FS interrupt flag
ANDCC #$EF ; Enable IRQ
PULS A, X
RTI
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INFL LDA CHS
SUBA #100
BNE INFL
LDA screen1+8
EORA #$FF
STA screen1+8
LDA CFS
SUBA #100
BNE INFL
LDA screen1+16
EORA #$FF
STA screen1+16
BRA INFL
Ok, I have two question:
i) I disabled the HS interrupt and I kept the ISR as above. I was surprised to see that the HS flag is always '1', so the counter CHS is being increased (at the rate of the FS). Is that supposed to be the right behaviour? Why is the flag '1' at all?
ii) I need to know the exact timing of both the HS and FS sync signals. Where can I get that information for Dragon 32 and Dragon 64?
Cheers