Update on progress - the ATX machine is running, I have everything except the cartridge port, real time clock and expanded audio built and working.
The keyboard interface is waiting on a single chip to arrive (basically an Arduino performing the translation of a PS2 keyboard's serial data into something usable)
I'm working on a revised video board that hugely simplifies things for PAL and NTSC (waiting on some bird seed SMD parts). This uses a very small CPLD to replace the mass of logic chips that pad NTSC video timing into PAL instead. The board also replaces the LM1889 video encoder, replacing it with the much more modern AD724 or AD725 encoder. These give superb, clean composite output but also generate separate luma and chroma signals for S-video and as a bonus the input to the AD chips is RGB so I've put together a circuit that translates the native YUV output of the 6847 into RGB (a similar trick is used on the SECAM version of the Dragon and if this version I've built doesn't work I will be adopting the SECAM circuit!)
The boards that run the CPU, SAM, RAM and ROM (currently two cards) are next in line so I can use one of Ciaran's SAMx8 plug-ins. The result is a single board instead of two and a much more capable build
I'm leaving the audio expansion card 'til last - the goal is one or two AY-3 sound generators. Bizarrely I've been sent a bunch of full AY-3-8910 chips (thank you Leslie) that means I can test the expansion itself and the emulated version of the AY-3-8913 chip I'm planning to use in separate steps
I say the audio card is last but this is also not quite the end of the story - the backplane for the ATX build has a huge area given over to plugging in a ready-to-roll FPGA board that provides an AMD Artix-7 chip (the same as used in the Spectrum Next phase 2) and a massive amount of memory. This isn't to replace the CPU (although it could), instead the goal is to replace the SAM/RAM/ROM sub-system so I can really go to town and create something comparable to the CoCo Deluxe or CoCo3. The FPGA also allows me to exploit the extra speed available through a HD63C09 without messing up the video output, effectively bumping the clock speed up to four times that of the original design while allowing the same hardware to run at the original clock speed if you want. The FPGA also unlocks the foundations for the plans I have on an expanded VDG setup. I had planned on doing this as a separate video board but I've since realised that having it inside the FPGA means I could potentially exploit the wider data bus between the FPGA and its RAM to simplify the video timing I had sketched out, or to double the video bandwidth again (my time slicing had the video at 1xClk or 2xClk irrespective of whether the CPU was 1x, 2x or 4x). In real terms that means even in the highest resolution I was planning for you would have 4 bits per pixel (from a 16 colour palette). Knocking the resolution down (2x1) either means 8 bits per pixel using a palette of 512 possible colours or direct 323RGB. Right now my head is still spinning with possibilities
