Alongside testing the SuperBoB, some of you will no doubt have seen my postings about 6809 code and the JCB Speech Synthesiser module. I've been using that as an example application on SuperBoB, with a possible view to selling the main speech synthesiser parts either alongside SuperBoB or separately. A YM2149 example application would also be a good candidate.
I've learnt a lot from this process. The main thing has been that it's not always possible to do away with the PIA on smaller CPLD implementations. Even just trying to simulate the B-side of the PIA sees me running out of space on these CPLDs (44-pin 9536/9572), due to the way I've configured SuperBoB (full address bus decoding). That makes me think that two versions of SuperBoB would be best. One 'pro' version with a larger CPLD (pin and macro-cell wise), and the smaller version you see in the picture. A new version would need to change CPLD type though, as the Xilinx ones are about to go obsolete. The existing SuperBoBs though, as a developer board are fine, and I have reasonable stock of those CPLDs.
Anyway, I've been in contact with the original author of the JCB Speech Synthesiser module, and he has said that as long as I am not charging for his code, I am welcome to redistribute it (changing it if necessary), which is good news for the example application.
So what couldn't I manage to emulate about the PIA with the smaller CPLD and the JCB SS program? Quite simply, it relates to the usage of the data bus buffers in the PIA. To save on 6809 instructions, the code often just INCs or DECs one of the ports in use. But with a minimal PIA implementation, those port buffers are not complete - so apart from bit 0, complete gobbledygook is written to the SPO256 chip. Hence I am going to modify the original JCB SS code and see if I can get it working with the smaller CPLD that way.
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