Dragon Beta

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Pernod70
Posts: 100
Joined: Sat Apr 22, 2017 10:06 pm
Location: Croydon, UK

Dragon Beta

Post by Pernod70 »

The emulation of the Beta last worked in MESS 0.138, which was 10 years ago! The MAME framework has advanced significantly since then but the Beta driver has been left to rot.

I'd really like to get the Beta emulation working again, but will require more or less a rewrite to make use of the latest MAME functionality.

Does anyone (Phill?) have any notes they can share on it's functionality, especially on the memory banking and how the two 6809's work together?

A couple of specific questions:
- Do both 6809's always see the same memory map?
- How is control passed from one 6809 to the other?
prime
Posts: 258
Joined: Fri Apr 10, 2009 1:40 am

Re: Dragon Beta

Post by prime »

Pernod70 wrote: Mon Dec 07, 2020 11:43 pm The emulation of the Beta last worked in MESS 0.138, which was 10 years ago! The MAME framework has advanced significantly since then but the Beta driver has been left to rot.

I'd really like to get the Beta emulation working again, but will require more or less a rewrite to make use of the latest MAME functionality.

Does anyone (Phill?) have any notes they can share on it's functionality, especially on the memory banking and how the two 6809's work together?
I'll have a look and dig out my notes.
A couple of specific questions:
- Do both 6809's always see the same memory map?
- How is control passed from one 6809 to the other?
Yes both 6809s see the same memory map.

One of the PIAs is connected to the /HALT line on the second CPU, so the first can wake it up when it has work to do.

I'll attach my research.txt file which may proove helpfull.
research.txt
(9.25 KiB) Downloaded 148 times
Memory Map.txt
(1.36 KiB) Downloaded 152 times
Cheers.

Phill.
Pernod70
Posts: 100
Joined: Sat Apr 22, 2017 10:06 pm
Location: Croydon, UK

Re: Dragon Beta

Post by Pernod70 »

prime wrote: Thu Dec 17, 2020 6:06 pm I'll attach my research.txt file which may proove helpfull.
Thanks for those, the area of interest is:
2005-05-24

I think I have just realised how the two processors interact, at startup the halt line on the second
CPU is active, so the first cpu takes over and initialises the hardware, since they share the same busses,
they also share the same vectors. When the first processor does some disk IO, it enables the second CPU
which goes into a loop that either copies data from ram->fdc or from fdc->ram, this seems to be mediated by
FIRQ which goes to both processors. The first enters a loop that does nothing except check for the INTRQ
from the WD, when it gets this I presume it halts the second CPU. This is weird, both processors are
running code from the SAME ROM !

Does bit 7 of FCC0, control the reset or one of the inturrupt lines on the second CPU ?

2005-05-26

I Think I now know how the second CPU is used.

On startup cpu #2 is halted.
During the init code cpu #2 is un-halted, it executes code from the rom, up until it hits a sync

When cpu #1 needs cpu #2 to do some work :-
stores io/address, transfer address, and read/write flag in low memory
through one of the pias, generates an NMI to cpu #2,
CPU #1 then goes into a loop syncing to inturrupt, and exits when
INTRQ from the WD comes.

Meanwhile :-
CPU #2 wakes up and picks up saved data from low memory
CPU #2 enters a synced loop, using each sync (generated by WD DRQ), to transfer a
byte to/from IO. after last byte transfered sync sends it to sleep until
woken again by NMI from CPU #1
Are both CPU's really running code from the ROM at the same time? Wouldn't that cause conflicts on the data bus? Is CPU#1 ever HALTed?

The current code has a comment saying FIRQ goes to both processors, confirmed by your notes, but the old working emulation never seemed to do this.

I'll see if I can make some more sense of this over the holidays.
prime
Posts: 258
Joined: Fri Apr 10, 2009 1:40 am

Re: Dragon Beta

Post by prime »

Pernod70 wrote: Fri Dec 18, 2020 12:53 pm Are both CPU's really running code from the ROM at the same time? Wouldn't that cause conflicts on the data bus? Is CPU#1 ever HALTed?

The current code has a comment saying FIRQ goes to both processors, confirmed by your notes, but the old working emulation never seemed to do this.

I'll see if I can make some more sense of this over the holidays.
As far as I can tell from the partial schematics that we have both of the CPUs have their TSC (three state control) pins controlled by external logic, meaning that whilst one is accessing the bus the other is prevented from doing so. Also remember whilst CPU #2 is active CPU #1 is wating for a SYNC, basically meaning it's sitting there internally twiddling it's fingers until it gets an interrupt.

I do have partial schematics, and BIOS listings if they would help.

Cheers.

Phill.
Last edited by prime on Sat Dec 19, 2020 12:42 pm, edited 1 time in total.
dragondata
Posts: 9
Joined: Tue Jun 22, 2010 8:51 pm
Location: Wilts
Contact:

Re: Dragon Beta

Post by dragondata »

Hi, I own the Beta board Phill did the original MESS emulation from. Whist Phill has more in-depth tech knowledge, I’ll try and help out where I can.
Pernod70
Posts: 100
Joined: Sat Apr 22, 2017 10:06 pm
Location: Croydon, UK

Re: Dragon Beta

Post by Pernod70 »

Thanks both, I'll keep you posted. I really think it's a missing interrupt issue as both CPU's are currently sat on different SYNC's during floppy transfer.
tjewell
Posts: 309
Joined: Mon Oct 19, 2009 4:58 pm
Location: Cambridge, England

Re: Dragon Beta

Post by tjewell »

Interesting! I think this is also how the Fairlight CMI works (the big 80's sampler beloved of The Art of Noise, and a zillion others). That has dual 6809s, and it was described to me (some 35 years ago) that the two processors both see the same memory, and somehow work in tandem to double the speed of the system. I was always surprised this had never been used anywhere else - this is the first time I've heard of it outside of the Fairlight. (Machines like the Fujitsu FM7 have two 6809s, but they're quite separate, with one acting like a dumb terminal running the video display and keyboard, the other running Basic or OS/9).

The Fairlight is an intriguing machine - basically a 64K 2x6809 system running OS/9 - and talking to another eight 6809 machines sharing a backplane, each with another 64K, each one being a sound channel. I have schematics somewhere ... anyway, going off an a tangent here :)
Pernod70
Posts: 100
Joined: Sat Apr 22, 2017 10:06 pm
Location: Croydon, UK

Re: Dragon Beta

Post by Pernod70 »

tjewell wrote: Tue Jan 19, 2021 12:26 am The Fairlight is an intriguing machine - basically a 64K 2x6809 system running OS/9 - and talking to another eight 6809 machines sharing a backplane, each with another 64K, each one being a sound channel. I have schematics somewhere ... anyway, going off an a tangent here :)
The CMI IIx is already in MAME and works to an extent, I'll take a look at it for some inspiration.
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