Hi,
Are you aware if it is possible to know when a new graphics screen starts being displayed on the TV? I'd like to implement double buffering to avoid flickering while drawing things on the screen. I checked the book "Inside the Dragon" but I couldn't figure it out (by the way, the book is great). It seems that all I can do is setting the graphics mode and the graphics page, but there is nothing about TV sinchronization signals (I take is VSYNC what I need). I'm not too optmistic about it...
Many thanks,
Gabriel
Double buffering
Re: Double buffering
Yep, you can have an IRQ triggered either at the falling or rising edge of the FS signal from the VDG. The level falls at the end of the active area and rises 57 scanlines later (this would be 32 scanlines, but the Dragon PAL circuitry stops the VDG clock to insert extra lines).
You want interrupts enabled from the B side of PIA0 and disabled on the A side (that would give you horizontal sync instead). So clear bit 0 of $FF01 (disable HS IRQs) and set bit 0 of $FF03 (enable FS IRQs) - this is how BASIC will have it set up anyway.
Clear bit 0 of $FF03 to get IRQs on the falling edge (end of active area), set it for the rising edge ("later" - er, maybe 63 scanlines before the beginning of active area in the next field).
From there you can have an IRQ service routine handle things, but that's slow - lots of overhead stacking. Better would be to mask interrupts from being serviced (ORCC #$50) then either poll bit 7 of $FF03 (which will be set when an IRQ occurs - ie a read will be negative) or use the SYNC instruction to halt until the next interrupt (which will be recognised, even if it's not serviced). The SYNC instruction has the lowest overhead, but you get to do things while waiting for the IRQ if you poll.
Remember to clear the source of the interrupt by reading from the PIA side's data register ($FF02 in this case), or you won't get subsequent ones.
You want interrupts enabled from the B side of PIA0 and disabled on the A side (that would give you horizontal sync instead). So clear bit 0 of $FF01 (disable HS IRQs) and set bit 0 of $FF03 (enable FS IRQs) - this is how BASIC will have it set up anyway.
Clear bit 0 of $FF03 to get IRQs on the falling edge (end of active area), set it for the rising edge ("later" - er, maybe 63 scanlines before the beginning of active area in the next field).
From there you can have an IRQ service routine handle things, but that's slow - lots of overhead stacking. Better would be to mask interrupts from being serviced (ORCC #$50) then either poll bit 7 of $FF03 (which will be set when an IRQ occurs - ie a read will be negative) or use the SYNC instruction to halt until the next interrupt (which will be recognised, even if it's not serviced). The SYNC instruction has the lowest overhead, but you get to do things while waiting for the IRQ if you poll.
Remember to clear the source of the interrupt by reading from the PIA side's data register ($FF02 in this case), or you won't get subsequent ones.
Re: Double buffering
Thank you sixxie, this is just great.
I promise I will post a link to my first test program.
Cheers!
Gabriel
I promise I will post a link to my first test program.
Cheers!
Gabriel