Hi Steve
Pictures deleted as requested mate.
My Dragon is one of the newer models (the box has the colour picture of a family playing chess on their dragon on it) but I also have an older one in the loft although I didn't check the game on it as the picture isn't very good with that one.
Thanks again for solving the problem though mate
Craig
Hungry Horace (Melbourne House version)
-
samplefiend
- Posts: 44
- Joined: Thu Sep 03, 2009 5:53 pm
Re: Hungry Horace (Melbourne House version)
Thank you!samplefiend wrote: Pictures deleted as requested mate.
Re: Hungry Horace (Melbourne House version)
I've tried this site's wave of Horace Goes Skiing on my Dragon 32 and found no problems. Craig, I note that you used an LCD screen, I used a CRT TV, could that be the difference?
Steve, my Dragon does have an Issue 2 motherboard so if it is a motherboard problem rather than a display screen technology problem then it is not the Issue 2 motherboard that is at fault. For more details about my D32 look at the entry for ID 78 at the bottom of this survey page http://www.studio68.no/surveys/dragon/default.asp
Steve, my Dragon does have an Issue 2 motherboard so if it is a motherboard problem rather than a display screen technology problem then it is not the Issue 2 motherboard that is at fault. For more details about my D32 look at the entry for ID 78 at the bottom of this survey page http://www.studio68.no/surveys/dragon/default.asp
Re: Hungry Horace (Melbourne House version)
OK, Thanks! I will leave this one for the hardware experts.
I will leave this one for the hardware experts.Re: Hungry Horace (Melbourne House version)
That's quite interesting...
So there's a write to the data direction register followed one cycle later by selecting the peripheral data register. Separating out those writes slightly fixes the problem. Sounds like the "DDR access" change takes effect before the output data is latched. Or the data hangs around even after the change. Very odd.
Looking at the data sheet, the lowest spec for the 6821 is a minimum cycle time of 1µs - plenty to fit in with any Dragon CPU's cycle time unless it were in fast or address-dependent mode - and I don't see the code switching to either of those in a trace. Maybe your PIA1 is just faulty? I wonder what would happen if you blew a fan over it.
There's a lot of "assumes part was deselected during the previous E pulse" in the data sheet, but all associated with changes to the Cx2 lines, not data/direction registers. Still, could be that it requires a cycle of E to be deselected in order for clear a latch somewhere. But if that's the case, why wouldn't this happen on *all* Dragons? I wonder if anyone has any good ideas about this...
Edit: Hitachi's HD6821 datasheet has a lot more information, though of course it's not necessarily the same hardware (seems likely though). It actually explicitly details using this programming method under "PIA Programming Via The Index Register" (page 16).
So there's a write to the data direction register followed one cycle later by selecting the peripheral data register. Separating out those writes slightly fixes the problem. Sounds like the "DDR access" change takes effect before the output data is latched. Or the data hangs around even after the change. Very odd.
Looking at the data sheet, the lowest spec for the 6821 is a minimum cycle time of 1µs - plenty to fit in with any Dragon CPU's cycle time unless it were in fast or address-dependent mode - and I don't see the code switching to either of those in a trace. Maybe your PIA1 is just faulty? I wonder what would happen if you blew a fan over it.
There's a lot of "assumes part was deselected during the previous E pulse" in the data sheet, but all associated with changes to the Cx2 lines, not data/direction registers. Still, could be that it requires a cycle of E to be deselected in order for clear a latch somewhere. But if that's the case, why wouldn't this happen on *all* Dragons? I wonder if anyone has any good ideas about this...
Edit: Hitachi's HD6821 datasheet has a lot more information, though of course it's not necessarily the same hardware (seems likely though). It actually explicitly details using this programming method under "PIA Programming Via The Index Register" (page 16).