The SN74LS783/MC6883 is designed to support 4K x 1, 16K x 1 and 64K x 1 (128 column refresh) dynamic RAMs. The SN74LS785 has been modified to support the above listed products as well as 16K x 4 and 64K x 1 (256 column refresh) dynamic RAMs.
Double Speed?
Re: Double Speed?
The 2nd paragraph on the datasheet has the answer to the 64K RAM question. However I think the 256 column refresh came sooner in a version of the MC6883.
Re: Double Speed?
Intriguing! I didn't have that version of the data sheet; had always been referring to the one in Inside the Dragon.
And yeah, it would have to have actually appeared in the LS783, as I think Dragon 64s still have those.
ISTR trying to transplant an LS785 from a CoCo many years ago and it not working - same pinout, it seems, but perhaps slightly different behaviour.
I see there's an extra RAM organisation in there too (16K x 4) - I shall have to implement that in XRoar
Edit: Aha! 'Devices manufactured after January 1, 1983 allow both "Fast" and "Slow" MPU rates to be used with Map Type "TY = 1"' - this explains a lot, and is not in the version I've typically referred to!
And yeah, it would have to have actually appeared in the LS783, as I think Dragon 64s still have those.
ISTR trying to transplant an LS785 from a CoCo many years ago and it not working - same pinout, it seems, but perhaps slightly different behaviour.
I see there's an extra RAM organisation in there too (16K x 4) - I shall have to implement that in XRoar
Edit: Aha! 'Devices manufactured after January 1, 1983 allow both "Fast" and "Slow" MPU rates to be used with Map Type "TY = 1"' - this explains a lot, and is not in the version I've typically referred to!
Re: Double Speed?
The CoCo 2 (or at least some of them) use the x 4 RAM chips.
Re: Double Speed?
Ok, back to the RAM refresh. So, 8 consecutive addresses until 256 have been processed? So that would be done in the first 32 scanlines of the display during the border draw.
<edit>
I'm guessing the SAM is triggering the 2nd RAM bank for half of that 256.
<edit>
I'm guessing the SAM is triggering the 2nd RAM bank for half of that 256.
Re: Double Speed?
The following information was copied from the NDUG 64K upgrade document...
Finally, thc SAM controls the 'refreshing' of the RAM chips., Dynamic RAM chips have a simple structure of one transistor and capacitor per bit (or cell), and the charge leaks away from the capacitor over a few tens of milliseconds. The RAMs are so constructed however that everytime a row address is presented to them, all the cells with this row address have their infomation read out into buffers - later in the cycle this information (or new infomation if there is a write-to—memory) is read back into the capacitors, so that the whole row is refreshed at once. The SAM inserts a series of these 'RAS-only refresh cycles' from time-to-time to keep all the cells updated. As a final subtlety, not all 256 RAS combinations need to be addressed on most chips, only 128. However some chips (notably the Texas 4161) do require 256 refresh addresses, and cannot be refreshed bv the 6883.
Re: Double Speed?
Looks to me like it only needs to refresh 128 addresses.
Re: Double Speed?
512-bit "rows" then. And indeed, finding a data sheet for the HM4864P (as in both of my D64s), it says only 128 addresses required. Perhaps normal 4164s (as in the D64 data sheet) are the same and I just found the data for some strange variety.