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I have no way of testing this at the moment so was hoping someone might already know the answer.

What happens on the 6809 if an NMI interrupt from the expansion/cartridge connector is triggered while the CPU is in the process of a fetch-decode-execute cycle? i.e. Is the current instruction completed before the NMI is detected or does it break the cycle?

Cheers.

It takes about 3 CPU cycles before any interrupt is recognised at all (and I *think* that also applies to NMI), and it won't interrupt an instruction. There's a flow chart starting on page 14 of the data sheet that seems to be pretty accurate.

Edit: won't interrupt instruction apart from SYNC & CWAI, of course!

Cheers Sixxie, might get away with this after all.