Brand new Hitachi 63x09E chips are available to buy from http://www.cloud9tech.com/ and several other online sources.
The following information explains the 63x09E chip in more detail...
The complete document is attached to this post along with others.HD63B09EP Technical Reference Guide
By Chet Simpson
Additions by Alan DeKok
Introduction
The HD63B09EP microprocessor by Hitachi, is a MC68B09E compatible
chip containing additional registers and an additional instruction set.
The 6309 was thought to be a flakey chip though, because it would
sometimes crash or change the values of registers when it encountered an
addressing mode or opcode invalid to the 6809. This was later found to be
an extended instruction set and a feature that would trap some programming
errors and jump to a specified location in memory.
Hitachi licensed the rights of the 6809 instruction set from
Motorola to make a 6809 compatible chip. When they finished the design,
they found there was a lot of unused space in the chip. With this in mind
they added extra registers and expanded on the instruction set, but due to
the licensing agreement with Motorola, they were unable to release the
information about the extra features.
Not only did the chip have an expanded instruction set, but it also
had a native mode that would run many of the instructions in fewer clock
cycles and a mode select for the FIRQ (Fast Interrupt ReQuest) that would
enable it to opperate the same as the IRQ.
In fact, all new instructions will execute in emulation mode, which
was originally seen when 'illegal' 6809 instructions produced odd results
when run on a computer with a 6309 installed.
The additional instruction set was first written about in the April
1988 issue of "Oh!FM", a Japanese magazine, and was later brought to
the attention of the 6809 community by Hirotsugu Kakagawa. He followed
up a series of '6809-6309 differences' messages on comp.sys.m6809 by
posting a detailed
explanation of the new features and instructions of the 6309.
This opened a whole new door to those who wished to
use the 6309 in place of the 6809.
The information in this reference is of technical nature and makes no
attempt to teach assembly language programming. It is ONLY a technical
reference guide for those who already know assembly and wish to use these
features in their programs. Although all of the opcodes for the 6309/6809
chip are listed in the appendix, only the additional features supplied by
the 6309 will be discussed in detail.
Summary of Features
More registers:
one 8/16 bit 'zero' register
Two 8bit accumulators.
One 16bit concatenated register
One 16bit value register.
One 8bit mode/error register.
One 32bit concatenated register
Two modes: MC68B09E emulation mode and HD63B09EP native mode.
Reduced execution cycles when running in native mode.
Many additional instructions.
Error trapping of illegal instructions and zero divisions.
HD63B09EP Technical Reference Guide Page 2
Description of Additional Registers
The 6309 has 7 additional registers. Only 4 of these are actual
registers. 2 are combinations of registers, and the last is a
constant-value register. These registers are:
ACCE - 8 bit accumulator.
ACCF - 8 bit accumulator.
W - 16 bit concatenated register (ACCE and ACCF combined).
Q - 32 bit concatenated register (ACCA, ACCB ,ACCE and ACCF
combined).
V - 16 bit register (which can only be accessed with the
inter-register instructions).
0 - zero register
MD - 8 bit mode/error register.
ACCE and ACCF both work in much the same manner as the ACCA and ACCB
accumulators. This makes for easier programming in math and data oriented
routines.
The W register is like the D register in the 6809. It is a
concatenated register containing the values of ACCE and ACCF as one 16 bit
value. ACCE is contained in the high 8 bits and ACCF is contained in the
low 8 bits.
The Q register is a 32 bit concatenated register. This register
is composed of the concatenation of D and W, which in turn are composed of
the registers ACCA, ACCB, ACCE and ACCF respectively. This register is used
mostly with the additional math instructions supplied with the 6309 which
will be discussed later.
The V register is a 16 bit register that can only be accessed with
inter-register instructions such a TFR and EXG. The contents of this
register will not change if the CPU is reset, allowing this register to be
used as a constant value for the program.
The 0 register is always zero, independant of writes to it.
It enables a zero value to be used in inter-register operations without
accessing memory, or changing the value of another register.
The MD register is a mode and error register and works much in the
same way as the CC register. The bit definitions are as follows:
Write bits
Bit 0 - Execution mode of the 6309.
If clear ( 0 ), the cpu is in 6809 emulation mode.
If set ( 1 ), the cpu is in 6309 native mode.
Bit 1 - FIRQ mode
If clear ( 0 ), the FIRQ will occur normally.
If set ( 1 ) , the FIRQ will operate the same as the
IRQ
Bits 2 to 5 are unused
Read bits - One of these bits is set when the 6309 traps an error
Bit 6 - This bit is set ( 1 ) if an illegal instruction is
encountered
Bit 7 - This bit is set ( 1 ) if a zero division occurs.
HD63B09EP Technical Reference Guide Page 3
Modes of Operation
The 6309 has two modes of operation; 6809 Emulation mode in which
the chip acts and executes instructions the same as the 6809, and 6309
Native mode which stores an extra two bytes on the stack when an interrupt
(IRQ) occurs, and executes instructions in fewer clock cycles.
When in native mode, the W register (2 additional bytes) is stored
(PSHS) on the system stack when an interrupt occurs, it is stored on the
stack right after the D (general data) register. Since ALL register
values are stored on the system stack when an IRQ (NOT FIRQ - See FIRQ
modes for more information) occurs, great care should be taken when
writing or patching those routines to run in native mode.
Pull <- CC,A,B,E*,F*,DP,Xhi,Xlo,Yhi,Ylo,Uhi,Ulo,PChi,PClo <- Push
* indicates the additional registers stored on the system stack
When in native mode those interrupt routines which modify the return
address by modifying the 10th and 11th byte offsets from the stack (STX
10,S or STY 10,S etc.) will have to be changed to modify the 12th and 13th
byte offsets from the stack (STX 12,S or STY 12,S etc.). If those routines
are not patched to run in native mode they will either get stuck in a
continuous loop or will crash the system due to the fact that they are not
returning to the correct address. This poses a MAJOR problem for OS-9
Level II since its main interrupt handling routine relies highly on the
changing of the return (PC) address on the stack. Disk read/write and
formatting routines also rely heavily on changing the return address
during an NMI (Non-Maskable Interrupt).
To patch those routines which do modify the return address, the
program or routine must be disassembled or modified with a disk sector
editing program. Look for instructions such as STX 10,S or STY 10,S that
has an RTI (Return from Interrupt) instruction within the next few lines
of the routine. The line containing STX 10,S or STY 10,S should be changed
to STX 12,S or STY 12,S respectively.
Remember, after those routines are patched, those programs using them
will NOT work in emulation mode and will require native mode to be enabled
upon startup.
Native Mode and Timing Loops
There is at least one more problem that needs to be addressed. Those
are routines which are dependant on timing loops for accuarate operation.
Since the 6309 executes instructions faster when in native mode, those
routines that use timing loops would be effected. Since this can pose a
problem and can create erratic operation, the delay value or routine will
need to be changed for the routine to operate correctly.
Those routines are usually serial-printer routines, cassette
read/write timimg routines, software clocks and some disk read/write
routines.
HD63B09EP Technical Reference Guide Page 4
Modes of the Fast Interrupt Request (FIRQ)
The designers of the 6309 decided that with the additional
instructions and native mode of operation, the FIRQ may be used more than
it usually is. With this in mind they decided to allow you to make the
FIRQ run the same as the IRQ and store (PSHS) all the current values of
the registers on the system stack. Normally, the FIRQ only stores the CC
(condition code) and the PC (Program Counter/return address) on the stack,
so to keep compatability with the 6809, they included it as a selectable
feature in the MD (Mode/status) register.
Inter-Register Instructions
The new Inter-Register instructions (ADCR, ADDR, CMPR, EORR, ORR,
SBCR, and SUBR) all work the same as their register/memory (ADCA, ADDA,
etc.) counterparts except that they operate between registers. All of the
new instructions use the same post-byte information as the normal TFR
instruction and use the format of R0,R1 (register 0 and Register 1
respectively) with the result going into R1. See Block Transfers for
information on the TFR block move instructions.
Mixed-size inter-register operations default to using
identical sized register. So TFR A,X actually executes as TFR D,X.
You could also do 'lea(d) d,pc' calculations by doing 'addr pc,d'. As
the new inter-register instructions can now perform math using the PC
register, REALLY odd possibilities exist. Try looking at code like
'eorr d,pc', and figuring out where it ends up.
Inter-register instructions with 16-bit r1 and CC or DP (8-bit r2)
are legal, but the results are unknown.
Bit Manipulation of Memory Locations
The AIM, EIM, OIM and TIM instructions all do logical bit
manipulations to locations in memory, with the result stored into the
location, and the respective bits for each instruction set in the CC
register. They can be used in the DIRECT, INDEXED or EXTENDED adressing
modes.
Instruction descriptions:
AIM - AND IN MEMORY
EIM - EOR IN MEMORY
OIM - OR IN MEMORY
TIM - TEST bits IN MEMORY
Instruction format: X, post byte, operand
Where X is the instruction op-code, post-byte contains the bits to
AND, OR, EOR or TEST against the memory location, and the operand is the
memory location or indexing post-byte depending on the mode of operation.
Mnemonic format:
Instruction logical operation value, memory location or index operation
Mnemonic example:
AIM #$0F,$E00
The example takes the contents of memory location $E00, does a LOGICAL
and with the Value #$0F and then stores the result back into $E00.