MK1 Dragon 32 hardware fault

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zephyr
Posts: 1474
Joined: Mon Jul 21, 2008 1:18 am

MK1 Dragon 32 hardware fault

Post by zephyr »

The MK1 Dragon 32 - Issue 2 boards (the ones with the added RAM patch boards) have a hardware fault which prevents memory above 16K being viewable via the VDG chip. The display appears very much like it does when running in POKE65497,0 double speed mode. Does anyone know why this happens, and if there is an easy fix?
sorchard
Posts: 530
Joined: Sat Jun 07, 2014 9:43 pm
Location: Norwich UK

Re: MK1 Dragon 32 hardware fault

Post by sorchard »

There are several pieces to this jigsaw:

The data input to the VDG doesn't come directly from the DRAM array but via IC13, an LS273 latch.

This latch is clocked by RAS0, one of the two row address strobes generated by the SAM.

The SAM has four memory size settings: 4K, 16K, 64K and 64K static.

The 16K mode supports two banks of 16K by using RAS0 for the lower 16K and RAS1 for the upper 16K. Thanks to IC13 being clocked by RAS0, the VDG can only ever see the lower 16K in this mode.

The 64K mode uses RAS0 only. RAS1 has a different function and is now Z7, an extra address line. The VDG can see the whole 64K in this mode.

The D32 ROM sets the memory size to either 16K or 64K according to a PIA input line. Reading this bit on a D32 (PEEK(&HFF22) AND 4) will tell you if the upper 16K can be used for video. If the input is low, then the mode is 64K and the video can be anywhere in memory.

Machines with 2 banks of 16K have the mode set to 16K. (e.g. MKII and ISS2 with memory daughterboard)

Machines with 32K implemented as, for example, 8 'half good' 64K chips have the mode set to 64K.

One possible 'fix' would be to AND together RAS0 and RAS1 and use this to clock IC13.

In general software should put the video display in the lower 16K for compatibility.
Stew
zephyr
Posts: 1474
Joined: Mon Jul 21, 2008 1:18 am

Re: MK1 Dragon 32 hardware fault

Post by zephyr »

Thanks for the information. :)
sorchard wrote: One possible 'fix' would be to AND together RAS0 and RAS1 and use this to clock IC13.
Any chance you could post a complete circuit diagam of this fix?
sorchard
Posts: 530
Joined: Sat Jun 07, 2014 9:43 pm
Location: Norwich UK

Re: MK1 Dragon 32 hardware fault

Post by sorchard »

I've made a sketch of the proposed mod though be warned I haven't looked at the board to see how best to do this. There's a chance the RAS0 trace doesn't stop at IC13 pin 11 and will need cutting in two places and linking to bypass the pin.

The wires from the daughter board should be kept short and it might be wise to insert a 22R resistor between the gate output and IC13 to suppress ringing. (The SAM outputs to the DRAM array have series resistors for this purpose)

It might be worth trying to drive IC13 pin 11 from E instead to see if that works before building a daughterboard. This might violate the VDG setup time but I'm not sure having not studied the timing diagrams very closely. (In fact I haven't checked that the delay introduced by the AND gate doesn't push things too far though it would be surprising if this stopped it working)

This should only be done on a Dragon that 'needs' it. It will make a complete mess of the display on a 64K mode D32.

The disclaimer is I've never tried this and haven't heard of anyone else trying it either.

An alternative fix would be to upgrade the machine to 64K ;-)
mod.jpg
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Stew
zephyr
Posts: 1474
Joined: Mon Jul 21, 2008 1:18 am

Re: MK1 Dragon 32 hardware fault

Post by zephyr »

Thanks for sharing the fix. 8-)
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