/HALT and buss access.
Posted: Wed Nov 04, 2015 6:06 pm
Hi All,
Does anyone know if it is possible for an external piece of hardware to use the processor bus whilst the /HALT signal is asserted? Basically what I want to try and do is this :
My hardware (DragonMMC) currently has an onboard AVR microcontroller, a CPLD some ROM and some RAM. What I want to do is eliminate the need for the ROM by having the microcontroller fill the RAM at boot time.
The reason for this is that all the other 'firmware' on the board is soft upgradable from the SD/MMC, the AVR had a bootloader which can update it's firmware, it can then update the CPLD firmware. But currently it cannot program the Dragon firmware.
Something like
On power on, assert HALT low, and wait a couple of cycles for the CPU to halt.
Have the AVR generate the address and data combinations to write the ROM code into the RAM.
Release halt and allow the CPU to continue, with the RAM mapped into the cart ROM space.
Is this likely to work?
Cheers.
Phill.
Does anyone know if it is possible for an external piece of hardware to use the processor bus whilst the /HALT signal is asserted? Basically what I want to try and do is this :
My hardware (DragonMMC) currently has an onboard AVR microcontroller, a CPLD some ROM and some RAM. What I want to do is eliminate the need for the ROM by having the microcontroller fill the RAM at boot time.
The reason for this is that all the other 'firmware' on the board is soft upgradable from the SD/MMC, the AVR had a bootloader which can update it's firmware, it can then update the CPLD firmware. But currently it cannot program the Dragon firmware.
Something like
On power on, assert HALT low, and wait a couple of cycles for the CPU to halt.
Have the AVR generate the address and data combinations to write the ROM code into the RAM.
Release halt and allow the CPU to continue, with the RAM mapped into the cart ROM space.
Is this likely to work?
Cheers.
Phill.