Hi All,
Does anyone know if it is possible for an external piece of hardware to use the processor bus whilst the /HALT signal is asserted? Basically what I want to try and do is this :
My hardware (DragonMMC) currently has an onboard AVR microcontroller, a CPLD some ROM and some RAM. What I want to do is eliminate the need for the ROM by having the microcontroller fill the RAM at boot time.
The reason for this is that all the other 'firmware' on the board is soft upgradable from the SD/MMC, the AVR had a bootloader which can update it's firmware, it can then update the CPLD firmware. But currently it cannot program the Dragon firmware.
Something like
On power on, assert HALT low, and wait a couple of cycles for the CPU to halt.
Have the AVR generate the address and data combinations to write the ROM code into the RAM.
Release halt and allow the CPU to continue, with the RAM mapped into the cart ROM space.
Is this likely to work?
Cheers.
Phill.
/HALT and buss access.
Re: /HALT and buss access.
You should be able to do anything you want once the bus becomes available. It sounds OK in principle though there could be one or two difficulties. The bus becomes available after the current op which could be quite a lot of cycles later. (Stacking or interrupt for example). So you would need to wait a large number of cycles and hope the bus doesn't do anything unpleasant while it's floating. Perhaps have a weak pullup on R/W? I was about to suggest using bus hold if the CPLD has that feature, but I'm not sure if R/W will always be high just before the bus is available.
There is a note in the 6809 datasheet saying that a halted state can be achieved during reset so that might be a way of getting hold of the bus cleanly on power up, before the CPU has a chance to do anything else. You won't be able to use the bus while in reset because A7 gets pulled low via a diode, possibly to prevent writes to SAM. Another thing to watch out for is reset rises slowly, meaning it's not well defined when everything comes out of reset, and you may need to experiment with delays before writing to various devices.
There is a note in the 6809 datasheet saying that a halted state can be achieved during reset so that might be a way of getting hold of the bus cleanly on power up, before the CPU has a chance to do anything else. You won't be able to use the bus while in reset because A7 gets pulled low via a diode, possibly to prevent writes to SAM. Another thing to watch out for is reset rises slowly, meaning it's not well defined when everything comes out of reset, and you may need to experiment with delays before writing to various devices.
Stew
Re: /HALT and buss access.
Another detail you've probably already twigged is that if you did capture the bus immediately on power up then you would be responsible for programming the SAM memory type bits.
Stew