archive.worldofdragon.org

Hmmm, those bars are at a higher frequency than what I had in mind, so probably not dram noise. As your photos show, that looks like the video clock coupling into the luma signal. If the noise is on the supply rails, then some bypass caps might help. I notice in the picture of your motherboard that ...

I've not seen your board type before so I'm not sure. Judging by the large size of the caps that have been fitted, this might be a known problem with this board layout. It might be worth adding some more bypass caps (100 - 220nF) across the dram supply rails on the back of the board just to see if i...

One thing that causes vertical bars, particularly bars that have the same spacing as text columns, is insufficient supply bypassing on the memory array. This motherboard picture in the archive is a good example: https://archive.worldofdragon.org/index.php?title=File:SA_8x64K.png Look at all those mi...

That demo does about represent the most that can be done in 20ms via the Dragon bus. To get a decent jump in performance would require something like building the whole screen image in external memory and copying it back. (Or not, and calling it a video card!) I think I was able to get over 60 of th...

So this is why you've been quiet Heh, I'm usually up to something ;) The design would fit into an XC95288XL, using up about 85%. That's the only 5V tolerant part I can think of off the top of my head. For an FPGA you're looking at 461 LUT4s & 150 flops. At 3V3 there are quite a few choices under £1...

Hi Rob! All the data is held in the Dragon's memory and the 6809 is animating the coordinates. Everything is happening at normal speed. The blitter is copying data from one place in the Dragon's memory to another, pixel-shifting it on the fly. The background is copied at a rate of two cycles per byt...

I had a sudden urge to do something ludicrous with the Dragon, so I hooked up an FPGA to the cartridge port. It was an ideal opportunity to experiment with some simple DMA-based graphics acceleration :) https://youtu.be/rYc-GtfMgfo https://gitlab.com/sorchard001/dragonblit I encountered the same flo...

I'm not on facebook so I've no idea what's been covered there e.g. I don't know what the 'streaming module' is. Is the /DSD signal the one that disables SAM's ls138 decoder? How is NMI presented, direct from the MSX hardware or via the CPLD? The perhaps relevant things that the MPI does is [1] buffe...

But why would it be causing any issues when the DMSX2 is effectively idle? I was thinking that maybe the DMSX2 was being addressed when it shouldn't because the mpu address bus is not always valid, but as you are gating via e this shouldn't be an issue. (The DOS addresses being so similar to the DM...

Just guessing because I know very little about any of the hardware involved... At the moment I suspect the differences between the DOS versions is down to a chance ordering of reads and writes, and/or stack contents when the hardware issue occurs. I assume nmi from the MSX side is disabled until req...