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The January 1984 issue of Color Computer Magazine has a pretty good picture of the Tano Dragon insides. It's probably just a Dragon 64 clocked for NTSC.
I like the board layout better than the CoCo.

Too bad they didn't socket the RAM, 6847 or PIAs.

The 6309 has functional differences so it's easy to detect. The A09 and B09 are the same functionally so I don't think there is any way to detect them in software.

My Tano Dragon has a 783.

Looks to me like it only needs to refresh 128 addresses.

Ok, back to the RAM refresh. So, 8 consecutive addresses until 256 have been processed? So that would be done in the first 32 scanlines of the display during the border draw.
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I'm guessing the SAM is triggering the 2nd RAM bank for half of that 256.

The CoCo 2 (or at least some of them) use the x 4 RAM chips.

The 2nd paragraph on the datasheet has the answer to the 64K RAM question. However I think the 256 column refresh came sooner in a version of the MC6883. The SN74LS783/MC6883 is designed to support 4K x 1, 16K x 1 and 64K x 1 (128 column refresh) dynamic RAMs. The SN74LS785 has been modified to supp...

Well, if that won't work then I guess there's no choice but to let the hardware do it.

Well, then it's not pages so mine won't work no matter what. It would have to be consecutive addresses and mine wasn't. In that case it would actually be easier. No ABX, just auto increment and we could use D. I don't know if you'd need to do this every interrupt or not. 20 LDX RefreshAdd 30 LDD ,X+...

I had thought that something like this would do the job... 10 ORG $5000 20 LDX #0 30 LDA ,-X 40 LOOP LEAX 256,X 50 LDA ,X 60 CMPX #$7FFF 70 BNE LOOP 70 JMP $9D3D Isn't this doing exactly what the hardware refresh does? If a page size is 256 bytes then that would do the trick (why decrement X and LE...